1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically, it relates to a clock supply technology employed to provide clock signals at the same phase to input/output circuits provided in the semiconductor integrated circuit.
2. Description of the Related Art
In parallel data transfer implemented between a plurality of semiconductor integrated circuits, data are normally input/output in synchronization with a reference clock signal. For instance, when inputting data in synchronization with the rise of the clock signal from level xe2x80x9cLxe2x80x9d to level xe2x80x9cH,xe2x80x9d the data to be transferred need to be sustained at a constant level over a specific length of time preceding and following the rise of the clock signal in order to transfer the data without error and with a high degree of reliability. The specific length of time elapsing before the rise is referred to as the setup time, whereas the specific length of time elapsing after the rise is referred to as the hold time.
As semiconductor integrated circuit technology has become more advanced, both the setup time and the hold time have been reduced to achieve a reduction in the length of time required for data transfer. However, unless clock signals achieving the same phase are provided to the input/output circuits utilized for data input/output, any reduction in the length of time required for data transfer is not achieved through reductions in the setup time and the hold time, in parallel data transfer. In other words, if the phases of clock signals provided to the individual input/output circuits are inconsistent, the actual data transfer cycle must be set by taking into consideration the inconsistency and, as a result, the length of time of data transfer increases.
At the same time, as the scale of integrated circuits is becoming larger, the routing through which clock signals are provided to the input/output circuits utilized for data input/output is becoming longer and more complex. In order to provide the clock signals to the individual input/output circuits while achieving uniform phase, methods such as devising a circuit arrangement that will equalize the lengths of supply routes and inserting a specific type of delay circuit in the clock supply route as necessary have been adopted in the prior art.
For instance, FIG. 2 is a block diagram of the semiconductor integrated circuit in the prior art which is disclosed in Japanese Unexamined Patent Publication No. 1998-228449.
This semiconductor integrated circuit comprises a drive-side semiconductor device 10 that outputs data and a reception-side semiconductor device 20 that receives the data.
The drive-side semiconductor device 10 is provided with a clock source 11 and a shift clock generating circuit. The clock source 11 generates a clock signal CLK. The shift clock generating circuit 12 generates a shift clock signal SCK achieved by shifting the phase of the clock signal CLK by a specific degree. The clock signal CLK and the shift clock signal SCK are provided to a switch 13 where either one of the signals is selected a mode signal MOD provided from the outside.
The drive-side semiconductor device 10 is also provided with an internal logic circuit 14 and a dummy output generating circuit 15. The internal logic circuit 14 generates output data. The dummy output generating circuit 15 generates dummy data to be used for adjustment. The output sides of the internal logic circuit 14 and the dummy output generating circuit 15 are connected to the input side of a switch 16 controlled by the mode signal MOD. The output side of the switch 16 is connected to the input sides of output circuits 17-0xcx9c17-n, utilized to output in parallel data with a plurality of bits to the reception-side semiconductor device 20. The output circuits 17-0xcx9c17-n, output data in synchronization with the clock signal CLK or the shift clock signal SCK selected at the switch 13.
The reception-side semiconductor device 20 is provided with a clock input circuit 21 and input circuits 22-0xcx9c22-n. The clock signal CLK from the drive-side semiconductor device 10 is provided to the clock input circuit 21, and the data with a plurality of bits are provided in parallel to the input circuits 22-0xcx9c22-n. The clock input circuit 21 generates and provides an internal clock signal ICK required in the reception-side semiconductor device 20 by using the clock signal CLK. The internal clock signal ICK is provided to timing adjustment circuits 24-0xcx9c24-n via a clock supply route 23. The individual timing adjustment circuits 24-0xcx9c24-n are respectively provided adjacent to the input circuits 22-0xcx9c22-n, and are utilized to provide the internal clock signal ICK to the individual input circuits 22-0xcx9c22-n, with almost the same timing by correcting differences in the length of transmission delay of the internal clock signal ICK occurring in the clock supply route 23. The timing adjustment circuits 24-0xcx9c24-n are each provided with a delay circuit that divides one cycle of the internal clock signal ICK into a plurality of equal portions, and the internal clocks ICK delayed by the individual delay circuits are sequentially selected to be provided to the corresponding input circuits 22-0xcx9c22-n.
In this type of semiconductor integrated circuit, the mode signal MOD is set to an adjustment mode over a specific length of time in elapsing, for instance, immediately after a power-up. This results in the shift clock signal SCK being selected at the switch 13 of the drive-side semiconductor device 10 and the dummy output generating circuit 15 being selected at the switch 16. As a result, dummy data for adjustment are output by the output circuits 17-0xcx9c17-n in synchronization with a rise of the shift clock signal SCK.
At the clock input circuit 21 of the reception-side semiconductor device 20, the internal clock signal ICK is generated based upon the clock signal CLK provided by the drive-side semiconductor device 10 and the internal clock signal ICK is provided to the timing adjustment circuits 24-0xcx9c24-n via the clock supply route 23. At the individual timing adjustment circuits 24-0xcx9c-24-n, clock signals for timing adjustment output by the delay circuits are sequentially selected and provided to the corresponding input circuits 22-0xcx9c22-n. Then, when the dummy data for adjustment provided by the output circuits 17-0xcx9c17-n at the drive-side semiconductor device 10 have been input in a normal state, the timing of the clock signals output by the individual timing adjustment circuits 24-0xcx9c24-n become fixed, thereby completing the timing adjustment for the clock signals.
When the specific length of time has elapsed after a power-up, the mode signal MOD is set in normal mode, thereby selecting the clock signal CLK at the switch 13 and selecting the internal logic circuit 14 at the switch 16 in the drive-side semiconductor device 10. Thus, a normal operation starts in which data generated at the internal logic circuit 14 are output through the output circuits 17-0xcx9c17-n in synchronization with a rise of the clock signal CLK.
At the individual input circuits 22-0xcx9c22-n at the reception-side semiconductor device 20, data input is performed in conformance to the clock signals provided by the individual timing adjustment circuits 24-0xcx9c24-n having undergone adjustment.
However, the following problems have yet to be addressed in the semiconductor integrated circuit in the prior art.
Namely, the timing adjustment processing must always be performed over a specific period of time after power-up by setting the adjustment mode with the mode signal MOD, and thus, normal operation cannot be started for the specific length of time. In addition, it is necessary to implement control for performing the adjustment processing, which complicates the structure of the control circuit.
An object of the present invention is to provide a semiconductor integrated circuit that achieves a reduction in the degree of inconsistency among delays by addressing the problems of the prior art discussed above and setting the delays at the individual delay circuits based upon transmission delay times that are actually measured.
In order to achieve the object described above, the semiconductor integrated circuit according to a first invention comprises a plurality of input terminals to which input data with a plurality of bits are provided in parallel with uniform timing, an input clock terminal to which an input clock signal indicating the timing for input data is provided, a plurality of means for input, each connected to one of the plurality of input terminals, to hold the input data provided to the corresponding input terminal with the timing of a rise or a fall of an internal input clock signal, a means for input clock distribution provided to distribute the input clock signal provided to the input clock terminal to the plurality of means for input and a plurality of adjustable means for input clock supply each provided between the means for input clock distribution and one of the means for input, that are utilized to generate internal input clock signals with uniform timing in synchronization with the input data to be provided to the individual means for input correcting differences in the length of delay of the input clock signals occurring in different distribution routes at the means for input clock distribution through connection/disconnection of elements inserted in series or in parallel.
The following advantage is achieved by assuming this structure.
The input clock signal provided to the input clock terminal is transmitted to the individual means for input clock supply via the means for input clock distribution. At the individual means for input clock supply to which the input clock signal is transmitted through different distribution routes at the means for input clock distribution with varying lengths of delay, the differences in the delay time are corrected and internal input clock signals achieving uniform timing are generated to be provided to the corresponding means for input. The input data with a plurality of bits are provided to the input terminals with uniform timing and then are input to the means for input connected to the input terminals. The input data are held with uniform timing at the means for input in conformance to the internal input clock signals.
In a second invention, the means for input clock supply according to the first invention are each provided with a circuit correction area where serial resistors can be inserted or shorted, parallel capacitors can be connected or disconnected or drive transistors can be connected or disconnected by correcting the circuit pattern utilizing a circuit correction device provided to correct an integrated circuit formed on a semiconductor substrate.
By adopting this structure, the following advantage is achieved at each means for input clock supply.
The delay time of the input clock signal transmitted to each means for input clock supply via the means for input clock distribution is corrected by the serial resistors, the parallel capacitors or the drive transistors in the circuit correction area, and the corrected input clock signal is provided to the corresponding means for input.
In a third invention, the means for input clock supply are each provided with an inversion amplifier unit that outputs a signal achieved by inverting the input clock signal provided by the means for input clock distribution, a first transistor connected between a source potential and a source terminal of the inversion amplifier unit, which supplies power to the inversion amplifier unit, a second transistor and a third transistor connected between the source potential and the source terminal of the inversion amplifier unit, the power supply by which the inversion amplifier unit is controlled in conformance with a first control signal and a second control signal respectively, a fourth transistor, a fifth transistor and a sixth transistor, a first control unit and a second control unit that are to be detailed below.
The fourth transistor, which is connected between a ground potential and a ground terminal of the inversion amplifier unit, supplies power to the inversion amplifier unit. The fifth and sixth transistors are connected between the ground potential and the ground terminal of the inversion amplifier unit, and the power supply to the inversion amplifier unit is controlled in conformance to a third control signal and a fourth control signal respectively. The first control unit, which is provided with a first fuse, implements control on the second and fifth transistors so as to sustain them in an ON state when the first fuse is not disconnected and outputs the first and third control signals to implement control on the second and fifth transistors so as to set them in an OFF state when the first fuse is disconnected. The second control unit, which is provided with a second fuse, implements control on the third and sixth transistors so as to sustain them in an OFF state when the second fuse is not disconnected and outputs the second and fourth control signals to implement control on the third and sixth transistors so as to set them in an ON state when the second fuse is disconnected.
In the third invention, the individual means for input clock supply function as follows.
The input clock signal transmitted via the means for input clock distribution to each means for input clock supply is inverted and amplified at the inversion amplifier unit which is connected to the source potential via the first through third transistors and connected to the ground potential via the fourth through sixth transistors to receive power. At this time, if the first fuse at the first control unit is not disconnected, the second and fifth transistors enter an ON state to supply power to the inversion amplifier unit together with the first and fourth transistors. If, on the other hand, the first fuse is disconnected, the second and fifth transistors are set in an OFF state and are cut off from the power supply. If the second fuse at the second control unit is not disconnected, the third and the sixth transistors enter an OFF state to become cut off from the power supply. If the second fuse is disconnected, the third and sixth transistors are set in an ON state to supply power to the inversion amplifier unit to together with the first and fourth transistors.
The semiconductor integrated circuit according to a fourth invention comprises a plurality of input terminals, an input clock terminal, a plurality of means for input, a means for input clock distribution, a plurality of means for input clock supply each provided between the means for input clock distribution and one of the means for input to generate an internal input clock signal based upon the input clock signal distributed by the means for input clock distribution to be provided to the corresponding means for input, and a plurality of output terminals, an output clock terminal, a plurality of means for output, a means for output clock distribution, a plurality of means for output clock supply and a means for data loop-back all of which are to be detailed below.
The output terminals output in parallel output data with a plurality of bits. An output clock signal indicating the timing with which the output data are output is provided to the output clock terminal. The means for output are each connected to one of the plurality of output terminals to output the output data to the corresponding output terminals in conformance to an internal output clock signal. The means for output clock distribution distributes the output clock signal provided to the output clock terminal to the plurality of means for output.
The means for output clock distribution distributes the output clock signal provided to the output clock terminal to the plurality of means for output. The means for output clock supply, each provided between the means for output clock distribution and one of the means for output, generate internal output clock signals based upon the output clock signal distributed by the means for output clock distribution and provide them to the corresponding means for output. When a test mode is specified by a mode signal used to specify either the test mode or a normal mode, the means for data loop-back provides the input data held at the means for input to the means for output as output data.
In the circuit structured as described above, the following operation is performed.
When the test mode is specified with the mode signal, the means for data loop-back connects the output sides of the means for input to the input sides of the means for output. In addition, the input clock signal provided to the input clock terminal is communicated to the individual means for input clock supply via the means for input clock distribution.
At each means for input clock supply, to which the input clock signal has been transmitted, an internal input clock signal is generated using the input clock signal and the resulting internal input clock signal is provided to the corresponding means for input. The input data with a plurality of bits are provided to the input terminals with uniform timing and then are input to the means for input connected to the input terminals. Then, at the means for input the input data are held in synchronization with the internal input clock signals. The input data held at the means for input are provided to the means for output as output data via the means for data loop-back.
In addition, the output clock signal provided to the output clock terminal is communicated to the individual means for output clock supply via the means for output clock distribution. At each means for output clock supply, to which the output clock signal has been transmitted, an internal output clock signal is generated using the output clock signal and the resulting internal output clock signal is provided to the corresponding means for output. The output data with a plurality of bits provided to the means for output are output to the output terminals with uniform timing in synchronization with the internal output clock signals.
According to a fifth invention, the means for input clock supply in the fourth invention are each provided with a plurality of first delay elements that can be disconnected, to generate internal input clock signals achieving uniform timing in synchronization with the input data and to provide them to the corresponding means for input by correcting differences in the delay time of the input clock signal occurring in different distribution routes at the means for input clock distribution. In the semiconductor integrated circuit adopting the structure, the following operation is performed at each means for input clock supply in the fourth invention.
The difference in the delay time of the input clock signal provided via the means for input clock distribution occurring in the distribution route at the means for input clock distribution is corrected by the plurality of first delay elements that can be disconnected, and an internal input clock signal achieving uniform timing in synchronization with the input data is generated. The internal input clock signal thus generated is provided to the corresponding means for input.
According to a sixth invention, the means for input clock supply in the fifth invention are each provided with a first inversion amplifier unit that outputs a signal achieved by inverting the input clock signal provided by the means for input clock distribution via the first delay elements, a second inversion amplifier unit constituted of a pair of complementary conductive transistors, i.e., a first transistor and a second transistor that further inverts the output signal from the first inversion amplifier unit to generate an internal input clock signal, a single or a plurality of conductive third transistors identical to the first transistor that are connected in parallel to the first transistor and can be cut off through fuse disconnection and a single or a plurality of conductive fourth transistors identical to the second transistor that are connected in parallel to the second transistor and can be cut off through fuse disconnection.
In the semiconductor integrated circuit adopting the structure described above, the following operation is performed at each means for input clock supply.
The difference in the delay time of the input clock signal provided via the means for input clock distribution occurring in the distribution route at the means for input clock distribution is corrected by the plurality of disconnectable first delay elements. Then, at the first and second inversion amplifier units, the delay time is corrected and the waveform is shaped to generate the internal input clock signal achieving uniform timing in synchronization with the input data. The internal input clock signal thus generated is provided to the corresponding means for input.
According to a seventh invention, the means for output clock supply in the fourth invention are each provided with a plurality of second delay elements that can be disconnected, to generate internal output clock signals achieving uniform timing and to provide them to the corresponding means for output by correcting differences in the delay times of the output clock signal occurring in different distribution routes at the means for output clock distribution.
In the semiconductor integrated circuit adopting the structure, the following operation is performed at each means for output clock supply.
The difference in the delay time of the output clock signal provided via the means for output clock distribution occurring in the distribution route at the means for output clock distribution is corrected by the plurality of second delay elements that can be disconnected, and an internal output clock signal achieving uniform timing is generated. The internal output clock signal thus generated is provided to the corresponding means for output.
According to an eighth invention, the means for output clock supply in the seventh invention are each provided with a third inversion amplifier unit that outputs a signal achieved by inverting the output clock signal provided by the means for output clock distribution via the second delay elements, a fourth inversion amplifier unit constituted of a pair of complementary conductive transistors, i.e., a fifth transistor and a sixth transistor, that further inverts the output signal from the third inversion amplifier unit to generate an internal output clock signal, a single or a plurality of conductive seventh transistors identical to the fifth transistor that are connected in parallel to the fifth transistor and can be cut off through fuse disconnection and a single or a plurality of conductive eighth transistors identical to the sixth transistor that are connected in parallel to the sixth transistor and can be cut off through fuse disconnection. In the semiconductor integrated circuit adopting the structure described above, the following operation is performed at each means for output clock supply.
The difference in the delay time of the output clock signal provided via the means for output clock distribution occurring in the distribution route at the means for output clock distribution is corrected by the plurality of disconnectable second delay elements. Then, at the third and fourth inversion amplifier units, the delay time is corrected and the waveform is shaped to generate the internal output clock signal achieving uniform timing. The internal output clock signal thus generated is provided to the corresponding means for output.
According to a ninth invention, a first means of delay having a plurality of third delay elements, which can be adjusted through disconnection and are utilized to insert a constant phase delay, is provided between the input clock terminal and the means for input clock distribution in the fourth invention.
In this structure, after the input clock signal provided to the input clock terminal is delayed through the third delay elements, it is provided to the means for input clock distribution to be distributed to the individual means for input clock supply.
According to a tenth invention, the means for input clock supply in the ninth invention are each provided with a fifth inversion amplifier unit that outputs a signal achieved by inverting the input clock signal provided by the means for input clock distribution, a sixth inversion amplifier unit constituted of a pair of complementary conductive transistors, i.e., a ninth transistor and a tenth transistor that further inverts the output signal from the fifth inversion amplifier unit to generate an internal input clock signal, a single or a plurality of conductive eleventh transistors identical to the ninth transistor that are connected in parallel to the ninth transistor and can be cut off through fuse disconnection and a single or a plurality of conductive twelfth transistors identical to the tenth transistor that are connected in parallel to the tenth transistor and can be cut off through fuse disconnection.
In the semiconductor integrated circuit adopting this structure, the following operation is performed.
The waveform of the input clock signal provided by the means for input clock distribution is shaped and its delay time is adjusted by the fifth and sixth inversion amplifier units and the resulting signal is provided to the corresponding means for input as an internal input clock signal.
According to an eleventh invention, a second means of delay having a plurality of fourth delay elements, which can be adjusted through disconnection and are utilized to insert a constant phase delay, is provided between the output clock terminal and the means for output clock distribution in the fourth invention.
In this structure, after the output clock signal provided to the output clock terminal is delayed through the fourth delay elements, it is provided to the means for output clock distribution to be distributed to the individual means for output clock supply.
According to a twelfth invention, the means for output clock supply in the eleventh invention are each provided with a seventh inversion amplifier unit that outputs a signal achieved by inverting the output clock signal provided by the means for output clock distribution, an eighth inversion amplifier unit constituted of a pair of complementary conductive transistors, i.e., a thirteenth transistor and a fourteenth transistor that further inverts the output signal from the seventh inversion amplifier unit to generate an internal output clock signal, a single or a plurality of conductive fifteenth transistors identical to the thirteenth transistor that are connected in parallel to the thirteenth transistor and can be cut off through fuse disconnection and a single or a plurality of conductive sixteenth transistors identical to the fourteenth transistor that are connected in parallel to the fourteenth transistor and can be cut off through fuse disconnection.
In the semiconductor integrated circuit adopting this structure, the following operation is performed.
The waveform of the output clock signal provided by the means for output clock distribution is shaped and its delay time is adjusted by the seventh and eighth inversion amplifier units and the resulting signal is provided to the corresponding means for output as an internal output clock signal.